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copyright ? cirrus logic, inc. 2011 (all rights reserved) http://www.cirrus.com ds734f5 oct '11 cs485xx family data sheet features ? cost-effective, high-performance 32-bit dsp ? 300,000,000 mac/s (multiply accumulates per second) ? dual mac cycles per clock ? 72-bit accumulators are the most accurate in the industry ? 24k x 32 sram, 2k blocks - assignable to data or program ? internal rom contains a variety of configurable sound enhancement feature sets ? 8-channel internal dma ? internal watch-dog dsp lock-up prevention ? dsp tool set w/ private keys for protecting customer ip ? configurable serial audio inputs/outputs ? configurable for all input/output types ? maximum 32-bit @ 192 khz ? supports 32-bit audio sample i/o between dsp chips ? tdm input modes (multiple channels on same line) ? 192 khz spdif transmitter ? multi-channel dsd direct stream digital sacd input ? supports two different input fs sample rates ? output can be master or slave ? dual processing path capability ? input supports dual domain slave clocking ? hardware assist time sampling for sample rate conversion ? integrated clock manager/pll ? can operate from external crystal, external oscillator ? input fs auto detection ? host & boot via serial interface ? configurable gpios and external interrupt input ? 1.8v core and a 3.3v i/o that is tolerant to 5v input ? low-power mode ? ?energy star ? ready? in low-power mode, 268 w in standby differentiating from the legacy cirrus multi-standard, multi-channel decoders, this new cs485xx family is still based on the same high-performance 32-bit fixed point digital signal processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associated with multi-channel and virtual-channel sound enhancements. target applications are: ? digital televisions ? multimedia peripherals ? ipod ? docking stations ? automotive head units ? automotive outboard amplifiers ? hd-dvd ? and blu-ray disc ? dvd receivers ? pc speakers there are also a wide variety of licensable dsp codes available today as seen by the following examples: cirrus also has developed, or is developing their own royalty-free versions of popular features sets like cirrus bass manager, cirrus dynamic volume leveler, cirrus original multichannel surround, cirrus virtual speaker & cirrus 3d-audio. the cs485xx family is programmed using the cirrus proprietary dsp composer ? gui development tool. processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio dsp primitives. the end result is a software image that is down-loaded to the dsp via serial host or serial boot modes. see section 6 for ordering information. cs485xx block diagram 32-bit dsp d m a p x y serial control 1 12 ch pcm audio out gpio debug watchdog tmr1 tmr2 pll s/pdif 12 ch. audio in / 6 ch. sacd in cs485xx
ds734f5 2 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the l atest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no responsibility is assu med by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other ri ghts of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not exte nd to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve po tential risks of death, personal injury, or severe property or environmental damage (?critical applicatio ns?). cirrus products are not designed, auth orized or warranted for use in products surgically implanted into the body, automoti ve safety or security devices, life su pport products or other critical applications . inclusion of cirrus products in such applicat ions is understood to be fully at the cu stomer?s risk and ci rrus disclaims and mak es no warranty, express, statutor y or implied, including the implied warranti es of merchantability and fitness for particular purpose, with regard to any cirrus product th at is used in such a manner. if the cust omer or customer?s cust omer uses or permit s the use of cirrus products in critical applications, customer agre es, by such use, to fully inde mnify cirrus, its officers, dir ectors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, dsp co mposer, and cirrus framework are trademarks of cirrus logic, inc . all other brand and product names in this document may be trademarks or service marks of their respective owners. dolby, dolby digitaol, dolby headphone, virtual speaker, and pro logic are registered trademarks of dolby laboratories, inc. su pply of an implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use the implementation in any finished end-user or ready-to-use final product. it is hereby notified that a license for such use is required from dol by laboratories. dts and dts neo:6 are registered trademarks of digital theater systems, inc. it is hereby notified that a third-party license f rom dts is necessary to distribute software of dts in any finished end-user or ready-to-use final product. srs, circle surround and trusurround xt are registered trademarks of srs labs, inc. circle surround ii is a trademark of srs la bs, inc. the circle surround technology is incorporated under license from srs labs, inc. the circle surround technology rights incorporated in the cs485xx are owned b y srs labs, a u.s. corporation and licensed to cirrus logic, inc. purchaser of cs485xx must sign a license for use of the chip and display of the srs labs tradema rks. any products incorporating the cs485xx must be sent to srs labs for review. the circle surround technology is protected under us and foreign patents issued and/or pen ding. circle surround, srs and (o) symbol are trademarks of srs labs, inc. in the united states and selected foreign countries. neither the purchase of the cs485xx, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any srs technology/solution. srs labs requires all set makers to comply with all rules and regulations as outlined in the srs trademark usage manual. spi is a trademark of motorola, inc. i2c is a trademark of philips semiconductor. ipod is a registered trademark of apple computer, inc. hd dvd is a trademark of dvd format/logo licensing corporation. blu-ray disc is a registered trademark of sony kabushiki kaisha corporation. energy star is a registered trademark of the environmental protection agency, a federal agency of the united states government.
3 ds734f5 table of contents 1 documentation strategy ...................................................................................................... ..................................... 1-5 2 overview .................................................................................................................... ................................................. 2-5 2.1 licensing ................................................................................................................. ........................................... 2-5 3 code overlays ............................................................................................................... ............................................. 3-6 4 hardware functional desc ription .............. ................ ................ ................. ................ .............. ............................... 4-7 4.1 dsp core .................................................................................................................. ......................................... 4-7 4.1.1 dsp memory .............................................................................................................. ............................... 4-7 4.1.2 dma controller .......................................................................................................... ................................ 4-7 4.2 on-chip dsp peripherals ................................................................................................... ................................ 4-7 4.2.1 digital audio input port (dai) .......................................................................................... .......................... 4-7 4.2.2 digital audio output port (dao) ......................................................................................... ....................... 4-8 4.2.3 serial control port (i 2 c ? or spi ? ) ............................................................................................................ 4-8 4.2.4 gpio .................................................................................................................... ..................................... 4-8 4.2.5 pll-based clock generator ............................................................................................... ....................... 4-8 4.2.6 hardware watchdog timer ................................................................................................. ...................... 4-8 4.3 dsp i/o description ....................................................................................................... .................................... 4-8 4.3.1 multiplexed pins ........................................................................................................ ................................ 4-8 4.3.2 termination requirements ................................................................................................ ........................ 4-8 4.3.3 pads .................................................................................................................... ...................................... 4-9 4.4 application code security ................................................................................................. ................................. 4-9 5 characteristics and specifications .......................................................................................... ................................ 5-9 5.1 absolute maximum ratings ......................... ......................................................................... .............................. 5-9 5.2 recommended operations condit ions ......................................................................................... ...................... 5-9 5.3 digital dc characteristics ........................ ........................................................................ ................................... 5-9 5.4 power supply characteristi cs .............................................................................................. ............................. 5-10 5.5 thermal data (48-pin lqfp) ................................................................................................ ............................ 5-10 5.6 switching characteristics?reset ........................................................................................... ....................... 5-11 5.7 switching characteristics?xti ............................................................................................. ........................... 5-11 5.8 switching characteristics?internal clock ...... ............................................................................ ...................... 5-11 5.9 switching characteristics?serial control port?spi slave mode .............................................................. ....... 5-12 5.10 switching characteristics?serial control port?spi master mode .. .......................................................... ..... 5-13 5.11 switching characterist ics?serial control port?i 2 c slave mode ................................................................... 5-13 5.12 switching characterist ics?serial control port?i 2 c master mode ................................................................. 5-14 5.13 switching characteristics?digital audio slave in put port ................................................................. ............ 5-15 5.14 switching characteristics?ds d slave input port ........................................................................... ............... 5-15 5.15 switching characteristics?digital audio output (dao) port ................................................................ ......... 5-16 6 ordering information ........................................................................................................ ....................................... 6-18 7 environmental, manufacturing, and handling information ...................................................................... ........... 7-18 8 device pinout diagrams .............................. ........................................................................ .................................... 8-19 8.1 CS48520, 48-pin lqfp pinout diagram ....................................................................................... ................... 8-19 8.2 cs48540, 48-pin lqfp pinout diagram ....................................................................................... ................... 8-20 8.3 cs48560, 48-pin lqfp pinout diagram ....................................................................................... ................... 8-21 9 package mechanical drawings ................................................................................................. .............................. 9-22 9.1 48-pin lqfp package drawing ............................................................................................... ......................... 9-22 10 revision history ........................................................................................................... ....................................... 10-23
4 ds734f5 list of figures figure 5-1. reset timing ....... ................ ................ ................ ................ ................ ................ ............................... 5-11 figure 5-2. xti timing......................................................................................................... .................................... 5-11 figure 5-3. serial control port?spi slave mode ti ming .......................................................................... ............... 5-12 figure 5-4. serial control port? spi master mode timing ......................................................................... .............. 5-13 figure 5-5. serial control port?i 2 c slave mode timing.......................................................................................... 5-14 figure 5-6. serial control port?i 2 c master mode timing........................................................................................ 5-15 figure 5-7. digital audio input (d ai) port timing diagram...................................................................... ................ 5-15 figure 5-8. direct stream digital?s erial audio input timing .................................................................... ............... 5-15 figure 5-9. digital audio output port timing, mast er mode...................................................................... .............. 5-17 figure 5-10. digital audio output timi ng, slave mode (relationship lrclk to sclk) ......................................... 5-17 figure 8-1. CS48520, 48-pin lqfp pinout............ ............................................................................ ...................... 8-19 figure 8-2. cs48540, 48-pin lqfp pinout............ ............................................................................ ...................... 8-20 figure 8-3. cs48560, 48-pin lqfp....................... ........................................................................ .......................... 8-21 figure 9-1. 48-pin lqfp packa ge drawing........................................................................................ ..................... 8-22 list of tables table 1-1. cs485xx family relate d documentation................................................................................ ................. 1-5 table 3-1. device and firmware selection guide ................................................................................. .................... 3-6 table 5-1. master mode (output a1 mode)........................................................................................ ..................... 5-16 table 5-2. slave mode (output a0 mode)......................................................................................... ...................... 5-17 table 6-1. ordering information ................................................................................................ .............................. 6-18 table 7-1. environmental, manufacturing, and handling information ... ........................................................... ....... 7-18
5 ds734f5 1 documentation strategy 1 documentation strategy the cs485xx family data sheet describes the cs485xx family of multichan nel audio processors. this document should be used in conjunction with the following documents when evalua ting or designing a system around the cs485xx family of processors. the scope of the cs485xx family data sheet is primarily the hardware specifications of the cs485xx family of devices. this includes hardware function ality, characteristic data, pinout, and packaging information. the intended audience for the cs485xx family data sheet is the system pcb designer, mcu programmer, and the quality control engineer. 2 overview the cs485xx dsp family is designed to provide high-perform ance post-processing and mixing of digital audio. the dual clock domain provided on the pcm inputs allows for the mixing of audio streams with different sampling frequencies. the low-power standby preserves battery life fo r applications which are always on, but not necessarily processing audio, such as automotive audio systems. there are three devices comprising the cs485xx family. th e CS48520, cs48540 and cs48560 are differentiated by the number of inputs and outputs available. all dsps support du al input clock domains and dual audio processing paths. all dsps are available in a 48-pin qfp package. refer to table 3-1 for the input, output, firmware features of each device. 2.1 licensing licenses are required for all of the third party audio processing algorithms listed in section 3 . contact your local cirrus logic sales representative for more information. table 1-1. cs485xx family related documentation document name description cs485xx family data sheet this document cs485xx family hardware user?s manual includes detailed system design information including typical connection diagrams, boot-procedures, pin descriptions, etc. an298?cs485xx family firmware user?s manual includes detailed firmware design information including signal processing flow diagrams and control api information dsp composer user?s manual includes detailed configuration and usage information for the gui development tool.
6 ds734f5 3 code overlays 3 code overlays the suite of software available for the cs 485xx family consists of an operating sy stem (os) and a library of overlays. the overlays have been divided into three main groups called matr ix-processors, virtualizer-pro cessors, and post-processors. all software components are defined below: 1. os/kernel ?encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, ca lling audio-processing subrouti nes, error concealment, etc. 2. matrix-processor ?any module that performs a matrix decode on pcm data to produce more output channels than input channels (2 ? n channels). examples are dolby prologic iix and dts neo:6. generally speaking, these modules increase the number of valid channels in the audio i/o buffer. 3. virtualizer-processor ?any module that encodes pcm data into fe wer output channels than input channels (n ? 2 channels) with the effect of provid ing ?phantom? speakers to represent the physical audio channels that were eliminated. examples are dolby headphone ? and dolby virtual speaker ? . generally speaking, these modules reduce the number of valid channels in the audio i/o buffer. 4. post-processors ?any module that processes audio i/o buffer pcm data in-place after the matrix- or virtualizer-processors. examples are bass managem ent, audio manager, tone control, eq, delay, customer-specific effects, etc. the bulk of each overlay is stored in rom within the cs485xx, but a small image is required to configure the overlays and boot the dsp. this small im age can either be st ored in an external serial flash /eeprom, or downloaded via a host controller through the spi ? /i 2 c ? serial port. the overlay structure reduces the time required to reconfig ure the dsp when a processing change is requested. each overlay can be reloaded independently without disturbing the other overlays. for example , when a new ma trix-processor is selected, the os, virtualizer-, and po st-processors do not need to be reloaded ? only the new matrix-processor (the same is true for the other overlays). table 3-1 lists the firmware available based on device selection. refer an298, cs485xx firmware user?s manual for the latest listing of appl ication codes and cirrus framework ? modules available. table 3-1. device and firmware selection guide device suggested application channel count input/output package CS48520-cqz digital tv, portable audio docking station, portable dvd, dvd mini/ receiver, multimedia pc speakers up to 4-channel in/4-channel out 48-pin qfp cs48540-cqz cs48540-dqz CS48520 features plus 8-channel car audio, dvd receiver up to 8-channel in/8-channel out 48-pin qfp cs48560-cqz cs48560-dqz cs48540 features plus 12-channel car audio, high-end digital tv, dual source/dual zone sacd up to 12-channel in/12-channel out 48-pin qfp
7 ds734f5 4 hardware functional description 4 hardware functional description 4.1 dsp core the cs485xx family dsps are single-core dsp with separate x and y data and p code memory spaces. the dsp core is a high-performance, 32-bit, user-programmable, fi xed-point dsp that is capable of performing two multiply-and-accumulate (mac) operations per clock cycle. the dsp core has eight 72-bit accumulators, four x- and four y-data registers, and 12 index registers. the dsp core is coupled to a flexible dma engine. the dma engine can move data between peripherals such as the serial control port (scp), digital audio input (dai) and digital audio output (dao), or any dsp core memory, all without the intervention of the dsp. the dma engine off loads data move instructions from the dsp core, leaving more mips available for signal processing instructions. cs485xx family functionality is controlled by application codes that are stored in on-board rom or downloaded to the cs485xx from a host controller or external serial flash/eeprom. users can develop their applications using dsp composer to cr eate the processing chain and then compile the image into a series of commands that are sent to the cs485xx through th e scp. the processing application can either load modules (matrix-processors, virtualizers, post-processors) from the dsps on-board rom, or custom firmware can be downloaded through the scp. the cs485xx is suitable for a variety of audio post-processi ng applications such as automotive head-ends, automotive amplifiers, and boom boxes. 4.1.1 dsp memory the dsp core has its own on-chip data and program ra m and rom and does not require external memory for post-processing applications. the y-ram and p-ram share a single block of memory that ca n be configured to make y and p equal in size, or more memory can be allocated fo r y-ram in 2kword blocks. 4.1.2 dma controller the powerful 8-channel dma controller can move data between 8 on-chip resources. each resource has its own arbiter: x, y, and p rams/roms and the peripheral bus. modulo a nd linear addressing modes are supported, with flexible start address and increment controls. the service intervals for ea ch dma channel, as well as up to 6 interrupt events, are programmable. 4.2 on-chip dsp peripherals 4.2.1 digital audio input port (dai) each version of the cs485xx supports a different number of input channels. refer to table 3-1 for more details. the dai port supports a wide variety of data input formats at sample rates (fs) as high as 192 khz. the port is capable of accepting pcm or dsd formats. up to 32 -bit word lengths are supported. dsd is supported and internally converted to pcm before processing. the dai also supp orts a time division multiplexed (tdm) one-line data mode, that packs pcm audio on a single data line (the total number possible depends on the ratio of sclk to lrclk and the version of chip. for example on the CS48520 only 4 ch of pcm are supported in one line mode and on the cs48560 up to 8 channels are supported.). the port has two independent slave-only clock domains. each data input can be independently assigned to a clock domain. the sample rate of the input clock domains can be de termined automatically by the dsp, off-loading the task of monitoring the spdif receiver from the ho st. a time-stamping feature allows the in put data to be sample-rate converted via software.
8 ds734f5 4.3 dsp i/o description 4.2.2 digital audio output port (dao) each version of the cs485xx supports a differ ent number of output channels. refer to table 3-1 for more details. dao port supports pcm resolutions of up to 32-bits. the port supports sample rates (fs) as high as 192 khz. the port can be configured as an independe nt clock domain mastered by the dsp, or as a clock slave if an external mclk or sclk/ lrclk source is available. one of the seri al audio pins can be re-configured as a s/pdif transmitter that drives a biphase encoded s/pdif signal (data with embedded clock on a single line). the dao also supports a time division multiplexed (tdm) o ne-line data mode, that packs multiple channels of pcm audio on a single data line. 4.2.3 serial control port (i 2 c ? or spi ? ) the on-chip serial control port is capable of operating as master or slave in either spi ? or i 2 c ? modes. master/ slave operation is chosen by mode select pins when t he cs485xx comes out of reset. the serial clock pin can support frequencies as high as 25 mhz in spi mode (spi clock speed must always be (f dclk /2)). the cs485xx serial control port also includes a pin for flow control of the communications interface (scp_bsy ) and a pin to indicate when the dsp has a message for the host (scp_irq ). 4.2.4 gpio many of the cs485xx peripheral pins ar e multiplexed with gpio. each gpio can be configured as an output, an input, or an input with interrup t. each input-pin in terrupt can be configured as rising edge , falling edge, active-low, or active-high. 4.2.5 pll-based clock generator the low-jitter pll generates integer or fr actional multiples of a reference frequen cy which are used to clock the dsp core and peripherals. through a second pll divider chain, a dependent clock domain can be output on the dao port for driving audio converters. the cs485xx defaults to running from the ex ternal reference frequency and is switched to use the pll output after overlays have been loaded and configured, either through master boot from an external flash or through host control. a built-in crystal oscillator circuit with a buffered output is provided . the buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.2.6 hardware watchdog timer the cs485xx has an integrated watchdog timer that acts as a ?health? monitor for the dsp. the watchdog timer must be reset by the dsp before the coun ter expires, or the entire chip is reset. this peripheral en sures that the cs485xx will reset itself in the event of a temp orary system failure . in stand-alone mode (that is, no host mcu), the dsp will reboot from external flash. in slave mode (that is, host mcu present) a gpio will be used to signal the host that the wa tchdog has expired and the dsp should be rebooted and re-configured. 4.3 dsp i/o description 4.3.1 multiplexed pins many of the cs485xx family pins are multi-function al. for details on pin func tionality, refer to the cs485xx hardware user?s manual . 4.3.2 termination requirements open-drain pins on the cs485xx must be pulled high for proper operation. refer to the cs485xx hardware user?s manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. mode select pins in the cs485xx family are used to select the boot mode upon the rising edge from reset. a detailed explanation of termination requirements for each co mmunication mode select pin can be found in the cs485xx hardware user?s manual .
9 ds734f5 4.4 application code security 4.3.3 pads the cs485xx i/os operate from the 3.3 v supply and are 5 v tolerant. 4.4 application code security the external program code may be encrypted by the programm er to protect any intellectual property it may contain. a secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. contact your local cirrus representative for details. 5 characteristics and specifications note: all data sheet minimum and maximum timi ng parameters are guaranteed over the rated voltage and temperature. all data sheet typical parameters are measured under the following conditions: t = 25 c, c l = 20 pf, vdd = vdda = 1.8 v, vddio = 3.3 v, gndd = gndio = gnda = 0 v. 5.1 absolute maximum ratings (gndd = gndio = gnda = 0 v; all vo ltages with respect to 0 v) warning: operation at or beyond these limits may result in perm anent damage to the device. normal operation is not guaranteed at these extremes. 5.2 recommended op erations conditions (gndd = gndio = gnda = 0 v; all vo ltages with respect to 0 v) note: it is recommended that the 3.3 v io supply come up ah ead of or simultaneously with the 1.8 v core supply. 5.3 digital dc characteristics (measurements performed under static conditions.) parameter symbol min max unit dc power supplies: core supply vdd ?0.3 2.0 v pll supply vdda ?0.3 3.6 v i/o supply vddio ?0.3 3.6 v |vdda?vddio| ? ? 0.3 v input pin current, any pin except supplies i in ?10ma input voltage on pll_ref_res v filt ?0.3 3.6 v input voltage on i/o pins v inio ?0.3 5.0 v storage temperature t stg ?65 150 c parameter symbol min typ max unit dc power supplies: core supply vdd 1.71 1.8 1.89 v pll supply vdda 3.13 3.3 3.46 v i/o supply vddio 3.13 3.3 3.46 v |vdda?vddio| ? ? 0 ? v ambient operating temperature t a ?? ? c ?cqz ? 0 ? +70 ? ?dqz ? ?40 ? +85 ?
10 ds734f5 5.4 power supply characteristics 5.4 power supply characteristics (measurements performed under operating conditions) 5.5 thermal data (48-pin lqfp) parameter symbol min typ max unit high-level input voltage v ih 2.0 ? ? v low-level input voltage, except xti v il ??0.8 v low-level input voltage, xti v ilxti ??0.6 v input hysteresis v hys ?0.4? v high-level output voltage (i o = ?2 ma), except xti v oh vddio*0.9 ? ? v low-level output voltage (i o = 2 ma), except xti v ol ??vddio*0.1v input leakage xti i lxti ?? 5 a input leakage current (all digital pins with internal pull-up resistors enabled) i leak ??70a parameter min typ max unit operational power supply current: vdd: core and i/o operating 1 1.dependent on application firmware and dsp clock speed. ? 203 ? ma vdda: pll operating ?8 ?ma vddio: with most ports operating ?27 ? ma total operational power dissipation: ? 480 ? mw standby power supply current: vdd: core and i/o not clocked ? 100 ? a vdda: pll halted ?1 ?a vddio: all connected i/o pins 3-stated by other ics in system ? 50 ? a total standby power dissipation ? 348 ? w parameter symbol min typ max unit junction temperature t j ??125 c thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 1.two-layer board is specified as a 76 mm x 114 mm, 1.6 mm thick fr-4 material with 1 oz. copper covering 20% of the top and botto m layers. 2.four-layer board is specified as a 76 mm x 114 mm, 1.6 mm thick fr -4 material with 1 oz. copper covering 20% of the top and bott om layers and 0.5 oz. copper covering 90 % of the internal power plane and ground plane layers. ja ? 63.5 ? c/watt ?54 ? thermal resistance (junction to top of package) two-layer board 3 four-layer board 4 3.to calculate the die temperature for a given power dissipation t j = ambient temperature + [(power dissipation in watts)* ja ] 4.to calculate the case temperat ure for a given power dissipation t c = t j ? [(power dissipation in watts)* jt ] jt ? 0.70 ? c/watt ?0.64 ?
11 ds734f5 5.6 switching characteristics?reset 5.6 switching characteristics?reset figure 5-1. reset timing 5.7 switching characteristics?xti figure 5-2. xti timing 5.8 switching characteristics?internal clock parameter symbol min max unit reset# minimum pulse width low t rstl 1?ms all bidirectional pins high-z after reset# low t rst2z ? 100 ns configuration pins setup before reset# high t rstsu 50 ? ns configuration pins hold after reset# high t rsthld 20 ? ns parameter symbol min max unit external crystal operating frequency 1 1.part characterized with the following crystal fr equency values: 11.2896, 12.288, 18.432, 24.576, & 27 mh.z f xtal 11.2896 27 mhz xti period t clki 33.3 100 ns xti high time t clkih 13.3 ? ns xti low time t clkil 13.3 ? ns external crystal load capacitance (parallel resonant) 2 2.c l refers to the total load capacitance as specified by the crystal manufacturer. crystals that require a c l outside this range should be avoided. the crystal oscillator circuit des ign should follow the crystal manufacturer? s recommendation for load capacitor selection. c l 10 18 pf external crystal equivalent series resistance esr ? 50 parameter symbol min max unit internal dclk frequency 1 f dclk ??mhz cs4852x-cqz cs4854x-cqz cs4856x-cqz cs4854x-dqz cs4856x-dqz f xtal f xtal f xtal f xtal f xtal 150 150 150 150 150 reset# t rst2z t rstl t rstsu t rsthld hs[3:0] all bidirectional pins t clkih t clkil t clki xti
12 ds734f5 5.9 switching characteristics?serial control port?spi slave mode 5.9 switching characte ristics?serial control port?spi slave mode figure 5-3. serial control port?spi slave mode timing internal dclk period 1 dclkp ? ? ns cs4852x-cqz cs4854x-cqz cs4856x-cqz cs4854x-dqz cs4856x-dqz 6.7 6.7 6.7 6.7 6.7 1/f xtal 1/f xtal 1/f xtal 1/f xtal 1/f xtal 1.after initial power-on reset, f dclk = f xtal . after initial kick-start commands, the pll is locked to max f dclk and remains locked until the next power-on reset. parameter symbol min typical max units scp_clk frequency 1 1.the specification f spisck indicates the maximum speed of the hardwar e. the system designer should be aware t hat the actual maximum speed of the communication port may be limited by the firmware application. fl ow control using the scp_bsy# pin should be implemented to pre vent overflow of the input data buffer. at boot the maximum speed is f xtal /3. f spisck ??25mhz scp_cs# falling to scp_clk rising t spicss 24 ? ? ns scp_clk low time t spickl 20 ? ? ns scp_clk high time t spickh 20 ? ? ns setup time scp_mosi input t spidsu 5??ns hold time scp_mosi input t spidh 5??ns scp_clk low to scp_miso output valid t spidov ?? 11ns scp_clk falling to scp_irq# rising t spiirqh ? ? 20 ns scp_cs# rising to scp_irq# falling t spiirql 0??ns scp_clk low to scp_cs# rising t spicsh 24 ? ? ns scp_cs# rising to scp_miso output high-z t spicsdz ?20 ?ns scp_clk rising to scp_bsy# falling t spicbsyl ?3*dclkp+20 ? ns parameter symbol min max unit scp_bsy# scp_cs# scp_clk scp_mosi scp_miso scp_irq# 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spibsyl t spiirql t spiirqh f spisck t spicsdz
13 ds734f5 5.10 switching characteristics?seri al control port?spi master mode 5.10 switching characteristics?serial control port?spi master mode figure 5-4. serial control po rt?spi master mode timing 5.11 switching characteristi cs?serial control port?i 2 c slave mode parameter symbol min typical max units scp_clk frequency 1 1.the specification f spisck indicates the maximum speed of the hardwar e. the system designer should be aware t hat the actual maximum speed of the communication port may be limited by the firmware application. f spisck ??f xtal /2 2 2.see section 5.7 . mhz scp_cs# falling to scp_clk rising 3 3.scp_clk period refers to the period of scp_clk as being used in a given application. it does not refer to a tested parameter. t spicss ? 11*dclkp + (scp_clk period)/2 ? ns scp_clk low time t spickl 20 ? ? ns scp_clk high time t spickh 20 ? ? ns setup time scp_miso input t spidsu 13 ? ? ns hold time scp_miso input t spidh 5? ?ns scp_clk low to scp_mosi output valid t spidov ?? 8ns scp_clk low to scp_cs# falling t spicsl 7? ?ns scp_clk low to scp_cs# rising t spicsh ? 11*dclkp + (scp_clk period)/2 ? ns bus free time between active scp_cs# t spicsx ? 3*dclkp ? ns scp_clk falling to scp_mosi output high-z t spidz ? ? 20 ns parameter symbol min typical max units scp_clk frequency 1 f iicck ?? 400khz scp_clk low time t iicckl 1.25 ? ? s scp_clk high time t iicckh 1.25 ? ? s scp_sck rising to scp_sda rising or falling for start or stop condition t iicckcmd 1.25 ? ? s start condition to scp_clk falling t iicstscl 1.25 ? ? s scp_clk falling to stop condition t iicstp 2.5 ? ? s bus free time between stop and start conditions t iicbft 3? ? s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ? ns hold time scp_sda inpu t after scp_clk falling t iich 20 ? ? ns ee_cs# scp_clk scp_miso scp_mosi 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spicsx f spisck t spidz t spicsl
14 ds734f5 5.12 switching characteristics?serial control port?i2c master mode figure 5-5. serial control port?i 2 c slave mode timing 5.12 switching characteristi cs?serial control port?i 2 c master mode scp_clk low to scp_sda out valid t iicdov ? ? 18 ns scp_clk falling to scp_irq# rising t iicirqh ? ? 3*dclkp + 40 ns nak condition to scp_irq# low t iicirql ? 3*dclkp + 20 ? ns scp_clk rising to scb_bsy# low t iicbsyl ? 3*dclkp + 20 ? ns 1.the specification f iicck indicates the maximum speed of the hardware. the system de signer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. fl ow control using the scp_bsy# pin should be implemented to pre vent overflow of the input data buffer. parameter symbol min max units scp_clk frequency 1 1.the specification f iicck indicates the maximum speed of the hardware. the system de signer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. f iicck ?400 khz scp_clk low time t iicckl 1.25 ? s scp_clk high time t iicckh 1.25 ? s scp_sck rising to scp_sda rising or falling for start or stop condition t iicckcmd 1.25 ? s start condition to scp_clk falling t iicstscl 1.25 ? s scp_clk falling to stop condition t iicstp 2.5 ? s bus free time between stop and start conditions t iicbft 3? s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ns hold time scp_sda inpu t after scp_clk falling t iich 20 ? ns scp_clk low to scp_sda out valid t iicdov ?18 ns parameter symbol min typical max units scp_bsy# scp_clk scp_sda scp_irq# 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb t iicirqh t iicirql 8 ack msb t iicstp 6 t iiccbsyl t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
15 ds734f5 5.13 switching characteristics? digital audio slave input port figure 5-6. serial control port?i 2 c master mode timing 5.13 switching characteristics? digital audio slave input port figure 5-7. digital audio input (dai) port timing diagram 5.14 switching characteris tics?dsd slave input port figure 5-8. direct stream digi tal?serial audio input timing parameter symbol min max unit dai_sclk period t daiclkp 40 ? ns dai_sclk duty cycle ? 45 55 % setup time dai_datan t daidsu 10 ? ns hold time dai_datan t daidh 5?ns parameter symbol min typ max unit dsd_sclk pulse width low t sclkl 78 ? ? ns dsd_sclk pulse width high t sclkh 78 ? ? ns dsd_sclk frequency (64x ov ersampled) ? 1.024 ? 3.2 mhz dsd_a/b valid to dsd_sclk rising setup time t sdlrs 20 ? ? ns dsd_sclk rising to dsd_ a or dsd_b hold time t sdh 20 ? ? ns scp_clk scp_sda 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb 8 ack msb t iicstp 6 t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr dai_sclk dai_datan t daidh t daidsu
16 ds734f5 5.15 switching characteristics?digital audio output (dao) port 5.15 switching characteristics?di gital audio output (dao) port figure 5-9. digital audio output port timing, master mode parameter symbol min max unit dao_mclk period t daomclk 40 ? ns dao_mclk duty cycle ? 45 55 % dao_sclk period for master or slave mode 1 1.master mode timing specifications ar e characterized, not production tested. t daosclk 40 ? ns dao_sclk duty cycle for master or slave mode 1 ?4060% table 5-1. master mo de (output a1 mode) 1 , 2 1.master mode timing specifications ar e characterized, not production tested. 2.master mode is defined as the cs48xx driving both dao_sclk, da o_lrclk. when mclk is an input, it is divided to produce dao_sc lk, dao_ lrclk. parameter symbol min max unit dao_sclk delay from dao_mclk ri sing edge, dao_mclk as an input t daomsck ?19 ns dao_lrclk delay from dao_sclk transition, respectively 3 3.this timing parameter is defined from the non-active edge of dao_ sclk. the active edge of dao_sclk is the point at which the data is valid. t daomstlr ?8 ns dao_sclk delay from dao_lrclk transition, respectively 3 t daomlrts ?8 ns dao1_data[3:0], dao2_data[1:0] delay from dao_sclk transition 3 t daomdv ?10 ns dao_mclk dao_sclk dao_lrclk daon_datan t daomclk t daomsck t daomstlr note: in these diagrams, falling edge is the inactive edge of dao_sclk.
17 ds734f5 5.15 switching characteristics?digital audio output (dao) port figure 5-10. digital audio output timing, slave mode (relationship lrclk to sclk) table 5-2. slave mode (output a0 mode) 1 1.slave mode is defined as dao_sclk, da o_lrclk driven by an external source. parameter symbol min max unit dao_sclk active edge to dao_lrclk transition t daosstlr 10 ? ns dao_lrclk transition to dao_sclk active edge t daoslrts 10 ? ns dao_dx delay from dao_sclk inactive edge t daosdv ?11 ns dao_sclk dao_lrclk daon_datan t daosstlr t daosclk dao_sclk dao_lrclk t daoslrts t daosdv t daosclk note: in these diagrams, falling edge is the inactive edge of dao_sclk.
18 ds734f5 6 ordering information 6 ordering information the cs485xx family part number is cs485ni-xyzr where: ? n?product number variant ? i?rom id number ? x?product grade ? y?package type ? z?lead (pb) free ? r?tape and reel packaging note: contact the factory for availability of the automotive grade package. 7 environmental, manufacturi ng, and handling information table 6-1. ordering information part no. grade temp. range package CS48520-cqz commercial 0 to +70 c 48-pin lqfp cs48540-cqz commercial 0 to +70 c cs48540-dqz automotive ?40 to +85 c cs48560-cqz commercial 0 to +70 c cs48560-dqz automotive ?40 to +85 c table 7-1. environmental, manufacturing, and handling information model number peak reflow temp msl rating 1 1.msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life CS48520-cqz 260 c 3 7 days cs48540-cqz cs48540-dqz cs48560-cqz cs48560-dqz
19 ds734f5 8 device pinout diagrams 8 device pinout diagrams 8.1 CS48520, 48-pin lqfp pinout diagram figure 8-1. CS48520, 48-pin lqfp pinout xto xti gnda pll_ref_res vdda (3.3v) gpio1 gpio2 gpio16, dai1_data0 gpio0 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, xmta gpio3, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk gpio18, dao_mclk dai1_sclk vdd1 gnd1 dao_sclk gpio4, hs2 reset# vddio1 gndio1 gpio6, dao2 _data0, hs3 gpio7, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, dai2_data0 CS48520 48-pin lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48
20 ds734f5 8.2 cs48540, 48-pin lqfp pinout diagram 8.2 cs48540, 48-pin lqfp pinout diagram figure 8-2. cs48540, 48-pin lqfp pinout xto xti gnda pll_ref_res vdda (3.3v) gpio1, dai1_data2 gpio2 gpio16, dai1_data0 gpio0, dai1_data1 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, xmta gpio3, dao1_ data1, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk gpio18, dao_mclk dai1_sclk vdd1 gnd1 dao_sclk gpio4, dao1_ data2, hs2 reset# vddio1 gndio1 gpio6, dao2_data0, hs3 gpio7, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, d ai2 _data0 cs48540 48-pin lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48
21 ds734f5 8.3 cs48560, 48-pin lqfp pinout diagram 8.3 cs48560, 48-pin lqfp pinout diagram figure 8-3. cs48560, 48-pin lqfp xto xti gnda pll_ref_res vdda (3.3v) gpio1, dai1_data2, tm2, dsd2 gpio2, dai1_data3, tm3, dsd3 gpio16, dai1_data0, tm0, dsd0 gpio0, dai1_data1, tm1, dsd1 38 40 41 42 43 45 46 gpio13, scp_bsy#, ee_cs# gpoi12, scp_irq# gpio10, scp__miso / sda gpio9, scp_mosi gpio11, scp_clk 35 33 31 30 28 26 25 gnd4 gndio4 vdd3 gnd3 vddio3 gndio3 23 22 21 19 17 15 1 gpio5, dao1_data3, x mta gpio3, dao1_ data1, hs1 dao1_data0, hs0 dao_lrclk dai1_lrclk, dai1_data4, dsd5 gpio18, dao_mclk dai1_sclk, dsd-clk vdd1 gnd1 dao_sclk gpio4, dao1_ data2, hs2 reset# vddio1 gndio1 gpio6, dao2 _data0, hs3 gpio7, dao2_d ata1, hs4 vdd2 gnd2 vddio2 gndio2 2 3 4 5 6 7 9 10 11 12 gpio8, scp_cs# test dbda dbck xtal_out gpio15, dai2_sclk gpio14, dai2_lrclk gpio17, dai2_data0, dsd4 cs48560 48-pin lqfp 8 13 14 16 18 20 24 27 29 32 34 36 37 39 44 47 48
22 ds734f5 9 package mechanical drawings 9 package mechan ical drawings 9.1 48-pin lqfp package drawing figure 9-1. 48-pin lqfp package drawing 48 ld lqfp (7 x 7 x 1.4 mm body) number of leads 48 min nom max a1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 d9.00bsc d1 7.00 bsc e0.50bsc e9.00bsc e1 7.00 bsc theta 0 7 l 0.45 0.60 0.75 l1 1.00 ref notes: 1) reference document: jedec ms-026 2) all dimensions are in millimeters and controlling dimension is in millimeters. 3) d1 and e1 do not include mold flash which is 0.25 mm max. per side.a1 4) dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
23 ds734f5 10 revision history 10 revision history revision date changes a1 july, 2006 advance release. a2 july, 2006 updated pinout definition for pins 26 and 27. updated typical power numbers. a3 december 5, 2006 updated sections 2.0, 4.21, 5.8, table 3, table 4, to show new device numbering scheme. updated sections 8.1, 8.2, 8.3. pp1 march 12, 2007 preliminary release pp2 december 18, 2007 changed title of data sheet from cs48500 data sheet to cs485xx family data sheet to cover all cs485xx family products. updated standby power specification in section 5.4 . updated dao timing specifications and timing diagrams in section 5.15 . f1 april 21, 2007 removed dsd phase modulation mode from section 5.14 . removed reference to mclk in section 5.14 . redefined master mode clock speed for scp_clk in section 5.10 . redefined dc leakage characterization data in section 5.3 . added typical crystal frequency values in table footnote 1 under section 5.7 . modified footnote 1 under section 5.9 . modified power supply characteristics in section 5.4 , f2 july 14, 2008 added reference to support for time division multiplexed (tdm) one-line data mode for dao port in section 4.2.2 . f3 february 16, 2009 updated section 5.5 , adding junction temperature specification. f4 june 29, 2011 updated section 5.10 ; changed t spidsu value to 13 ns. f5 october, 2011 updated section 5.15 dao output slave mode specifications.

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